When stress is applied to the channel within an active area of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered from their corresponding values for a transistor containing an unstressed semiconductor. This is because the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, the direction of the applied stress, and the type of carriers.
The effect of stress on the performance of semiconductor devices, especially on the performance of a metal-oxide-semiconductor field effect transistor (MOSFET, or a “FET” in short) device built on a silicon substrate, has been extensively studied in the semiconductor industry. For a p-type MOSFET (PMOSFET, or a “PFET” in short) utilizing a silicon channel, the mobility of minority carriers in the channel (which are holes in this case) increases under uniaxial compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an n-type MOSFET (NMOSFET, or an “NFET” in short) devices utilizing a silicon channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under uniaxial tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. Tensile stress in transverse direction, i.e., the direction perpendicular to the movement of carriers, can enhance both electron and hole mobilities. Thus, performance of field effect transistors may be improved by forming a stress-generating structure in or on a semiconductor substrate.
Methods of employing stress-generating shallow trench isolation liners in a bulk substrate are known in the art. Direct application of such methods to semiconductor-on-insulator substrate results in an insignificant amount of improvement in performance compared to bulk equivalents. This is because the thickness of a top semiconductor layer is much less than a depth of shallow trench isolation in bulk substrates, which may be from about 300 nm to about 450 nm, and the amount of stress transferred to SOI devices is proportional to the thickness of the top semiconductor layer, which may be from about 5 nm to about 30 nm in the case of ultra-thin semiconductor-on-insulator (UTSOI) substrates employed for high performance devices.
In view of the above, there exists a need for an effective stress-generating structure for semiconductor-on-insulator (SOI) devices, and methods of manufacturing the same.
Further, current semiconductor processing sequence used in industry employs silicon oxide as a trench fill material. Modification of an exposed structure of the trench isolation structure would require alterations to subsequent processing steps.
Therefore, there exists a need for an effective stress-generating structure that is compatible with existing semiconductor processing after formation of trench isolation structures, and methods of manufacturing the same.